I designed this clock over the course of two weeks for the Open 7400 Competition. The clock, which is made from 25 CD4000 ICs, three 555/556 ICs and a handful of discrete components, includes an alarm and a way of setting the clock that until now I have only seen implemented using microcontrollers. All this makes for a rather involved circuit, but I have split the schematic into a number of pages, which will hopefully make it easier to follow
The timebase is similar to many other clock designs published on line, but that's because this is by far the best way to do it. A standard 32.768KHz watch crystal is connected to the internal oscillator of a 4060, the output of which is divided down to 2Hz by the 4060's 14 binary divider stages. A final divider stage, made from one half of a 4013, gives a 1Hz signal which is used to run the clock. The timebase has two 1Hz outputs, one of which is always on and the other of which is gated by the RUN signal. This output is only enabled when the clock is running, stopping the clock whenever it is being set. The ungated output is used to make the display flash when the clock is not running.
The two diodes and resistor to the right of the schematic form an AND gate, which is used to gate the 1Hz signal. Most of the AND gates and all of the OR gates in this clock are built out of discrete components, rather than ICs. Not only does this save board space, something which I would have run out of if even one more IC was needed, it also allows the gates to be put exactly where they are needed, saving wiring.
At this point I should probably explain how you set the clock. Many digital clock designs on the internet simply have buttons to increase each digit, or a switch which makes the clock run faster. Instead, I chose to use a method that I have only ever seen implemented with a microcontroller. The clock has three setting buttons, the first of which (the Mode Select button) allows the user to select one of the three digits (hours, minutes or seconds, if any) to change. The second button increases the current digit by one, and the third button resets it to zero. There is also a fourth button, which turns the alarm on and off, and a fifth to reset the alarm. Four of these five buttons (all of them except the Alarm Reset button) need to be debounced. At first I tried using simple RC circuits to do this, but they were unreliable. Instead I decided to use monostables. Each monostable has a time constant of approximately 250mS, but this is not critical and the value needed will depend on the buttons you use. The circuit should work as shown with almost any button, but you may find the response to be a bit sluggish, in which case you might want to decrease the time period. I originally chose 100mS time periods, but this caused double triggering with the cheap buttons I used.
The clock has four modes: Set Hours, Set Minutes, Set Seconds and Run. Pressing the Mode Select button cycles through each of these modes by strobing the 4017's clock input. The 10nF capacitor and 10k resistor apply a short pulse to the 4017's reset pin at power on, ensuring that the clock always starts in Set Hours mode. This reset pulse is also fed to other parts of the clock that need to be reset at power on by the POR (power-on reset) line. The four outputs (HSET, MSET, SSET and RUN) are high when their corresponding mode is selected and low when any other mode is selected. The 4017 resets to Set Hours mode on every fourth press of the Mode Select button.
The RUN output is OR'd with the 1Hz signal from the timebase and fed to the FLASH output. This output makes the unselected digits flash when the clock is in one of the Set modes, or light constantly when the clock is running.
The seconds and minutes displays are driven by two identical counter circuits, which are wired to count to 59 before resetting back to 00. The first 4026 drives the units, and generates a pulse every 10 seconds (or 10 minutes) to clock the second 4026, which forms the tens counter. A 4017 is syncronised to the tens counter, and wired so as to reset the counters every 60 seconds (or 60 minutes), as well as clocking the next stage. The Q6 output is OR'd with the POR line, so that all three counter chips will be reset at power on. This ensures that the clock always starts at 00:00:00.
The 4019 is a quad AND-OR select gate, which switches various signal lines to alter the behaviour of the counters in each of the different modes. As it's not an especially widely used chip, it's probably worth explaining how the 4019 works before describing the circuit in detail. Of course, I would also recommend reading the 4019 datasheet for a more complete explanation. The 4019 has two banks of inputs (A1-A4 and B1-B4) and one bank of outputs (D1-D4). It also has two control inputs (Ka and Kb), which control input banks A and B respectively. Whenever Ka is high, the bank A inputs are sent to the outputs, and whenever Kb is high, the bank B inputs are sent to the outputs. The two control lines allow you to select between bank A, bank B, both banks OR'd together, or neither bank (in which case the outputs will be low).
In this clock, the 4019 is only used to select one bank or the other—never both or neither. One single line is used to control the 4019; this line is connected directly to the Kb input, and via a NOT gate to the Ka input. When the clock is in Set Seconds mode, the SSET line is high, so Kb is kept high and Ka is pulled low by the NOT gate, selecting the bank B inputs. When the clock is in any mode other than Set Seconds, the opposite happens and the bank A inputs are selected. The 4019 in the minutes counter functions in a similar way. This arrangement allows four different signal lines to be switched between two signal sources each:
The hours counter is largely the same as the seconds and minutes counters, but there are a few notable differences. The most important of these is the reset circuit, which must be triggered on 24 instead of 60. Resetting at 60 is easy enough because only the value of the tens counter is important—as soon it reaches 6, the count must be at 60. Resetting at 24 is more difficult because we have to take both digits into account. Fortunately this doesn't take any more ICs than in the other counters, because 4026s have a NOT 2 output. This sits high normally, then goes low whenever the counter is at 2. By simply inverting the NOT 2 output from the tens counter using a spare NOT gate in the 4069 chip, we get a signal that goes high whenever the clock is showing 20-something hours. Meanwhile, a 4017 is syncronised to the units counter (rather than the tens counter as previously), and its Q4 output is AND'd with the inverted NOT 2 signal to produce a signal that goes high at 24 hours, and can be used to reset the counters.
The second difference is the lack of clock output switching. No clock output is necessary from the hours counter, as there are no other stages needing a clock signal. The unused inputs on the 4019 are grounded, as is normal for unused CMOS inputs.
The time at which the alarm should go off is set in BCD using a set of DIP switches. This means that there is only one alarm to be set, but this is unlikely to be a problem in most applications. There is no reason that multiple banks of switches couldn't be included, as well as doubling up the XNOR and AND gates (see below), to allow for more alarms, but you would also need a way of controlling which of the alarms are enabled individually. Setting the alarm in BCD is a little tedious if you need to change it frequently, but setting it on the display would require a lot more circuitry. Perhaps if I'd had a bit more time (and breadboard space) before the competition deadline, I would have designed the extra circuits. I didn't bother to include switches to set the alarm to the second, as in my opinion this is unnecessary and would just cost more, both in money and in board space.
The circuit around the actual switches is relatively straight forward. In particular, note the use of pull-down resistors. Also, note how there are only three switches for the tens of minutes, whereas there are four for the units of minutes. This is because the tens of minutes only counts to six, so a fourth bit is unnecessary. Likewise, there are only two switches for the tens of hours, as this only counts to two.
The alarm on-off switching is handled by the other half of the 4013 IC used in the timebase. The flip flop is set up so that it's output will change state every time the Alarm On-Off button is pressed. There really isn't much to this part of the circuit.
This circuit detects when the clock is displaying the same number of minutes as selected on the BCD switches. A 4518 dual BCD counter, syncronised to the main minutes counters, gives the units and tens of minutes in BCD. Each bit is compared to the state of the corresponding switch by an XNOR gate, and the outputs of the XNOR gates are combined together using a 4068 8-input AND gate. A pair of 4077s are used for the XNOR gates, but as there are only 3 bits in the tens of minutes signal, one gate remains unused. One of the AND gate inputs is also unused, and is connected to V+.
At this point you may be wondering why I bothered using seperate counters to run the display and alarm. The answer is that I wasn't planning on building the alarm originally, and it was only added as an afterthought, after I had already bought the parts for the main clock. If I had planned it from the beginning, I would have used a single set of BCD counters, with some BCD to 7 segment converters to drive the displays.
The hours detector is almost identical to the minutes detector, besides it handling one less bit (as explained above). For this reason, there are two unused XNOR gates, and two spare inputs on the AND gate. These inputs are connected to the outputs of the minutes detector and the alarm on-off latch, so the output of this AND gate will only go high at the set time and when the alarm is enabled.
The first half of this circuit is a simple 555 monostable with a time constant of approximately 250 seconds, although this will vary a lot depending on the electrolytic capacitor used. It is triggered by the output of the alarm detection circuits, through a NOT gate as 555 inputs are active low. After it has been triggered, the monostable keeps the alarm running for a period of time before shutting it off automatically, so that it doesn't beep continually if left. The alarm can also be stopped at any time by pressing the Reset Alarm button.
The second half of the circuit is the alarm sequencer, based around a 4017. The sequencer's job is to make the alarm beep on and off, rather than running continually which would be very annoying. By connecting the beeper to outputs Q1 and Q3, and making the 4017 reset on Q6, it produces two beeps followed by a short gap. Note that the beeper doesn't sound on Q0; this is because when the alarm is not running, the 4017 is continually reset, keeping Q0 on. The reset input (MR) needs to be held high normally, and low when the alarm should sound. This is the opposite of the 555's output, so a NOT gate is used to invert the signal. Finally, the beeper is controlled by a switching transistor. I used a 2N4401 here because I have plenty of them, but almost any NPN transistor would do. If you use a low current beeper, or a 555 that can supply a reasonable output current (such as the NE555), you may not need the transistor at. Simply connect the beeper directly to the cathodes of the two diodes, omitting the transistor and 10k resistor.